In non-volatile memory (NVM) devices, as the feature sizes of devices in the core region are reduced to less than 55 nm, the pitch of the active region (AA pitch) is reduced to less than 122 nm so that the process can no longer utilize the self-aligned process. The associated spacing of the control gate is reduced to 230 nm, after the deposition of the sidewall layer in the core region, the width of the sidewall will be reduced to less than 60 nm, resulting in a very high aspect ratio in the core region (greater than 6). Thus, depositing a nickel layer in the active region at the bottom of the core region to form a nickel silicide is a challenging process. Forming a metal silicide in the core region can reduce the surface resistance (Rs) of the contact hole (CT) and the surface resistance of the word line region (WL strap), which will improve the program cycle and erase cycle performance of a storage unit.
A conventional method for manufacturing a semiconductor device may include first forming a control gate in the core region by etching, then forming a gate in the peripheral region. The method may include performing an annealing process in the metal silicide in the peripheral region, and then performing an annealing process of the metal silicide in the core region. In this method, the sidewall may be a two-layer structure including silicon oxide/silicon nitride (ON) or a three-layer structure including silicon oxide/silicon nitride/silicon oxide (ONO).
In the prior art method, prior to forming a metal silicide, a wet etching process is performed to remove the native oxide, the bottom portion of the silicon oxide layer of the sidewall may be subjected to etching, which causes the etching solution to enter the tunnel oxide layer, thereby affecting the device performance.
Furthermore, because a metal silicide is first formed in the peripheral region, and an annealing process is performed thereon, thereafter, a metal silicide is formed in the core region following by an annealing process. Therefore, heat generated in the annealing process in the core region may affect a device in the peripheral region. Thus, it is very difficult to form a metal silicide in the core region while ensuring the device in the peripheral region is not affected by the additional heat.
In the conventional method for manufacturing a semiconductor device, the process of forming a metal silicide in the core region is different from that of forming a metal silicide in the peripheral region. A nickel metal silicide in the peripheral region is formed using two rapid thermal annealing (RTA) processes, the first RTA process is performed at a low temperature, so that nickel reacts with silicon to form nickel silicide (NiSi), the second RTA process is performed at a high temperature so that the nickel silicide is transformed from a high-impedance state to a low-resistance state. After titanium (Ti) or titanium nitride (TiN) is deposited in the contact hole in the core region, a annealing process is required to be carried out at 600° C. to 730° C. to form TiSi2.
Nickel metal silicide cannot withstand high temperature. Under high temperature, nickel silicide NiSi will be converted to NiSi2, which has a high resistance. However, forming a titanium silicide from titanium requires a higher temperature than forming a nickel silicide from nickel. When the temperature is higher than 600° C., the phase of the nickel silicide may be altered. Thus, in order to ensure that the phase of the nickel silicide will not be altered in the formation of titanium silicide, the annealing temperature of the titanium silicide should be less than 600° C., then titanium can only be converted to TiSi2 which has a resistance much larger than the resistance of the nickel silicide.
Thus, there is a motivation to provide a method for improving the quality and performance of a semiconductor device.